Packaging Sets the Ceiling on AI Accelerators: Why the Back End Became the Center of Gravity

Semiconductor manufacturing splits in two. The front end etches transistors into a wafer; the back end cuts, stacks, links, and tests the finished die into a package. True to the name, the back end was long treated as a low-value auxiliary step bolted onto the rear of the front end. Not anymore. The decisive constraint on how much AI hardware ships in 2026 is not wafer starts in the front end but packaging allocation in the back. The leading-edge front-end nodes are sold out too—but the constraint now setting the additional ceiling sits on the packaging side. When Nvidia GPUs run short, the cause is less that the logic die cannot be printed than that there is no packaging slot to bind that die with memory into a single block.

The Pieces of the Back End: What's What

The back end comes down to one question: how do you place many dies close together inside a single package? The closer they sit, the faster the signals between them travel and the better the power efficiency. The approaches split broadly into 2.5D—placing dies side by side—and 3D—stacking them upward.

Table sources: CoWoS structure — WikiChip (TSMC) / hybrid-bonding pitch and density — TSMC SoIC announcement (via Tom's Hardware) / UCIe — UCIe Consortium / as-of 2026-06. The "roughly 100x" is TSMC's figure for density per unit area; the linear pitch in the text (6µm vs 30–40µm) is a 5–7x ratio.

These parts do not run separately—they nest inside one package. A single Nvidia AI accelerator places a logic die and several HBM stacks side by side on a CoWoS interposer, and each of those HBMs is itself built by stacking DRAM in 3D. The back end is where all of this binding happens.

Why the Back End Became the Performance Engine

The answer lies on the front-end side. For decades, performance came from making transistors smaller—from Moore's law. When the cost and difficulty of that scaling hit a wall, the industry's standard roadmap (IRDS) shifted its axis. Call it "More than Moore": win density gains not from the transistor itself but from system integration—chiplets and 3D packaging.

The decisive technology here is hybrid bonding. Dies used to be linked by solder bumps (microbumps) spaced 30–40µm apart. Hybrid bonding removes the bumps and bonds copper directly to copper, narrowing the production pitch to 6µm. TSMC's roadmap targets 4.5µm in 2029, and 'SoIC-Next' targets 3µm in 2027.

This density matters because the 'wiring' between dies starts to approach the wiring density inside a chip. Dense enough, and two stacked dies behave, in effect, as a single chip. The boundary between chip and package blurs. The density gain the front end used to win by shrinking transistors, the back end now inherits by stacking dies. Integration became performance. The margin, the bottleneck, the control—every story in this piece follows from this one mechanism. Once the boundary dissolved, the money, the bottleneck, and the leverage were all drawn into the integration step that absorbed the performance.

This engine has a brake, though. The more you stack, the more the heat density per unit volume spikes. The practical ceiling on stack height is set first by the ability to pull heat out, not by the bonding pitch. As much as integration lifts performance, the next wall is heat.

The Margin Flowed to Memory

When the performance engine moves, the margin moves with it. The advanced-packaging market is projected to grow from roughly $45 billion in 2024 to roughly $79.4 billion in 2030, with 2.5D/3D expanding fastest at more than 20% a year (Yole projection). TSMC's advanced-packaging revenue is growing at roughly 80% a year as well. Its share of total revenue is still small, but it is the fastest-growing axis.

The picture is sharper on the memory side. HBM earns a far higher margin than ordinary DRAM, and it is sold out, its price locked in by forward contracts through 2026. The result is SK Hynix's 2026 first-quarter results.

Table source: SK Hynix 2026 first-quarter earnings release (via CNBC, ninescrolls), as-of 2026-04-23.

One quarter's operating profit surpassed an entire year's from two years earlier. What turned a memory company into this was not transistor scaling alone. The decisive factor was integration—stacking dies on top of DRAM-cell scaling (the front end) to push up bandwidth—that is, HBM. HBM is a collaboration between the front end and the back end, and the center of gravity of the newly added value tipped toward the stacking side.

Packaging Allocation Sets the Supply Ceiling

While the margin moved to the integration step, the supply ceiling came to be set there too. Building more AI accelerators requires CoWoS packaging slots—and those slots are short.

Table sources: CoWoS capacity and demand — siliconanalysts, oplexa compilation / Nvidia share — Digitimes / as-of 2026-Q1–Q2. Capacity and share are estimates/projections. Note the differing units: capacity is a monthly exit rate, demand is annualized.

Reconcile the numbers and it comes out like this. The 120,000–130,000 figure is monthly capacity—and an exit rate reached only at the end of 2026 at that. Average it over the year's ramp, and actual 2026 supply falls short of the 1-million-wafer annual demand. That is why expansion does not break the sellout. Nvidia alone holds roughly 60% of CoWoS and has pre-reserved more than half of the expansion, filling the lines years deep. So the ceiling on GPU supply is set first by packaging allocation, not by the front end that prints the logic die.

Packaging is not the only constraint, of course. HBM supply itself, ABF substrates, and power delivery are all tight at the same time. Nor is CoWoS the only answer—alternatives like Intel's EMIB and Foveros, Samsung's I-Cube, and glass interposers become the variables that could ease the bottleneck. Still, at this moment the binding constraint that hits the ceiling first is CoWoS allocation.

Nor does this back end finish inside a single company. A large share depends on OSATs (outsourced assembly and test), and roughly 73% of OSAT revenue is concentrated in Asia. ASE and Amkor together hold more than 40%, and the top three hold more than 60%. Trade friction is pushing a dispersion toward Malaysia, Vietnam, and the Philippines. Even TSMC outsources some of packaging's simpler steps to ASE and Amkor. That the bottleneck has shifted to the back end also means it is concentrated in particular regions and a handful of firms.

The Control Line Extended to HBM

When value and the bottleneck gather in the back end, that point becomes geopolitical leverage. Until now, semiconductor controls against China centered on front-end lithography equipment like EUV scanners. That equipment control stays in place—and the control line has extended one layer further, onto a back-end product.

In December 2024, the U.S. Commerce Department's BIS blocked exports of advanced HBM to China at the national level for the first time. The threshold: memory bandwidth density above 2GB/s/mm². The aim is to slow China's capacity to produce AI chips. The EUV-equipment control (front end) stays untouched, and a new product control was added on HBM—a back-end stacked memory. Just before the control took effect, Chinese firms including Huawei were reported to have stockpiled roughly 7 million Samsung HBM units (estimated at over $1 billion). The side trying to block and the side trying to stockpile had made the same judgment about what the target was.

A target draws a fierce contest for share. In the second quarter of 2026, the HBM market stood at SK Hynix 62%, Micron 21%, and Samsung 17%—Micron overtaking Samsung. Full HBM4 production begins in the third quarter of 2026, and SK Hynix is projected to take the majority of the HBM4 volume going into Nvidia's next-generation accelerators.

Table sources: same as each section above (see ## Sources below). The geopolitics row is an "addition," not a "shift" (EUV control retained + HBM control newly created).

A line has to be drawn clearly, though. The back end has not replaced the front end. HBM, and the logic die placed on top of CoWoS, are in the end products the front end printed, and the front end's leading-edge nodes are just as sold out. More precisely, the center of gravity tipped not toward a single process step called 'the back end' but toward two distinct points—memory (HBM) and integration (packaging). What changed is the value chain's center of gravity. The last step that lifts performance, and the margin, bottleneck, and leverage that step generates, moved from etching transistors to integrating dies.

So the signals to watch when reading AI silicon change too. As much as how many nanometers the process node is, it now matters just as much who got how much packaging allocation, how HBM share is moving, and where the export-control line is drawn.

Go one step further: that the center of gravity "moved" means it converged on a few integration players. Performance, margin, bottleneck, and control leverage condense into TSMC's packaging, SK Hynix's HBM, and a handful of Asia-concentrated OSATs. Who holds those positions creates more pricing power than a node race like N2—and, at the same time, greater single-point-of-failure risk. The node-scaling headline is closer to a lagging indicator.

The question that remains is whether this convergence is structural or a passing feature of the AI cycle's peak. SK Hynix's 72% operating margin may be a cycle peak that mean-reversion is hard to escape. Whether this shift reverses depends on how fast CoWoS expansion catches up to demand, when the HBM forward contracts expire, and when the sellout clears. The 'back' in back end, at least for now, marks order, not importance.